The NHi- 15671 is a low cost complete Multi-Protocol MIL-STD- Data Bus interface between a dual redundant bus and a host processor.
The device functions as a programmable Bus Controller, Remote Terminal, Bus Monitor and simultaneous Monitor/Remote Terminal. It contains a protocol chip, two monolithic transceivers and 64K word SRAM. The unit is available packaged in a .95" x .95" 69 pinceramic PGA, or .95" x .95" 68 pin ceramic quad flatpack.
The only external components required are two coupling transformers.The NHi-156XX appears to the host computer as 64K words of 16 bit wide memory controlled by standard RAM signals. The device can thus be easily interfaced with all popular processors and buses.
The built-in interrupt controller supports an internal FIFO which retains header information for queuing up to 6 pending interrupt requests plus an overflow interrupt.
All modes of operation access data tables via pointers residing in RAM which facilitates multiple buffering.This allows buffers to change without moving data and promotes efficient use of RAM space. The data tables have programmable sizes and locations.The NHi-156XX defaults to remote terminal operation on power up.
- Multi-Protocol Interface
- PCI bus or Local Bus interface to host processor
- Operates from 20 Mhz clock
- +5V monolithic transceivers
- +3.3v logic
- Appears to host as a Dual Port Double Buffered 64K x 16 SRAM
- Footprint less than 1 square inch
- Ensures integrity of all shared data and control structures
- Built- in interrupt controller
- Internal FIFO is configurable to retain header information for queuing up to 6 pending interrupt requests plus an overflow interrupt, or as a 7 interrupt revolving FIFO
- Provides interrupt priority input and output pins for daisy- chaining interrupt requests
- Contains a Timer Unit which provides 32 bit RTC (Real- Time- Clock) with 1, 2, 4, 8, 16, 32 and 64 uS internal, or user provided external clock resolution for data and event time tagging
- Selectable 768/ 672 us Failsafe Timer with complete Testability
- Double buffering of messages and data tables
- Low power CMOS technology
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